In recent years, as liquid crystal display devices with improved viewing angle characteristics, liquid crystal display devices of Multidomain Vertical Alignment mode (MVA mode) have been developed and used in liquid crystal TVs, etc. A liquid crystal display device of VA mode performs display in normally black mode by using a vertical alignment-type liquid crystal layer, in which liquid crystal molecules are aligned vertical to the substrate surface in the absence of an applied voltage, in combination with a pair of polarizing plates arranged in a crossed-Nicols state via the liquid crystal layer.
As described in Patent Document 1, a liquid crystal display device of MVA mode includes linear-shaped domain regulating means provided on both sides of a liquid crystal layer to thereby regulate the azimuth direction in which liquid crystal molecules incline in the presence of an applied voltage, thus forming, in one pixel, a plurality of domains (multidomain) whose azimuth directions of orientation of the liquid crystal molecules (director) are different from each other. Such a structure including, in each pixel, domains (regions) whose azimuth directions of orientation are different from each other is referred to also as an “orientation-divided structure”. Four-domain structures are widely employed, in which four azimuth directions of orientation are arranged so that angles formed by polarization axes of polarizing plates arranged in a crossed-Nicols state are equally divided in two. By the employment of such orientation-divided structures, it is possible to achieve a wide viewing angle.
Furthermore, Patent Document 2 discloses a technique for improving the viewing angle dependence of γ characteristics of a liquid crystal display device of MVA mode. The γ characteristics represent the gray scale dependence of the display brightness, and the γ characteristics having viewing angle dependence means that the display brightness proportion with respect to the maximum brightness when an image of a certain gray level is viewed from the front differs from that when viewed obliquely. If the display brightness proportion with respect to the maximum brightness differs depending on the viewing direction, it presents a problem, especially when displaying images such as photographs or displaying television broadcasts and the like. The technique disclosed in Patent Document 2 is a technique whereby a first sub-pixel and a second sub-pixel included in each pixel exhibit different brightnesses from each other at least at a certain gray level, and it is referred to also as a pixel division technique or a multi-pixel technique. The structure of a liquid crystal display device in which each pixel includes such first and second sub-pixels is referred to also as a pixel division structure or a multi-pixel structure.
Now, referring to FIG. 23, a liquid crystal display device in MVA mode having a multi-pixel structure disclosed in Patent Document 2 will be described. FIG. 23 is a schematic view showing two of a plurality of pixels arranged in a matrix pattern including a plurality of rows and a plurality of columns, with the two pixels being adjacent to each other in the column direction.
Each pixel P of a liquid crystal display device 900 includes two sub-pixels (a first sub-pixel SP-1 and a second sub-pixel SP-2). Pixels along the jth row are associated with a gate bus line Gj, and pixels along the ith column are associated with a source bus line Si. The first sub-pixel SP-1 is associated with TFT-1, and the second sub-pixel SP-2 is associated with TFT-2. The gate electrodes of TFT-1 and TFT-2 are both connected to the common gate bus line Gj, and are turned ON/OFF by the same gate signal voltage. The source electrodes of TFT-1 and TFT-2 are both connected to the common source bus line Si, and when TFT-1 and TFT-2 are turned ON, a source signal voltage is supplied from the common source bus line Si to the first sub-pixel SP-1 and the second sub-pixel SP-2.
Each of the first sub-pixel SP-1 and the second sub-pixel SP-2 included in each pixel P includes a liquid crystal capacitor and a storage capacitor. A liquid crystal capacitor is formed by a sub-pixel electrode, a liquid crystal layer, and a counter electrode opposing the sub-pixel electrode via the liquid crystal layer. The storage capacitor is formed by a storage capacitor electrode electrically connected to the sub-pixel electrode, an insulating layer (e.g., a gate insulating layer), and a storage capacitor counter electrode opposing the storage capacitor electrode via the insulating layer. The storage capacitor electrode may be the sub-pixel electrode itself. The storage capacitor counter electrode may be a part of a CS bus line (referred to also as a storage capacitor bus line or a storage capacitor line), or may be formed integrally with a CS bus line. In FIG. 23, each sub-pixel electrode is connected to the drain electrode of the corresponding TFT, and is arranged so as to partially overlap with the corresponding CS bus line, thereby forming the storage capacitor thereof.
The first sub-pixel SP-1 of a pixel along the jth row is associated with a CS bus line CS-A, and the second sub-pixel SP-2 of a pixel along the jth row is associated with a CS bus line CS-B. The CS bus lines CS-A and CS-B are electrically independent of each other. Therefore, by controlling the CS voltages (referred to also as storage capacitor signal voltages) supplied from the CS bus lines CS-A and CS-B, the brightness exhibited by the first sub-pixel SP-1 may be made different from the brightness exhibited by the second sub-pixel SP-2, as shown below.
For example, an image write pulse (gate ON pulse) of a gate signal supplied to the gate bus line Gj rises, and a source signal voltage having a positive polarity is supplied to the pixel at jth row, ith column. When the source signal voltage of the positive polarity is supplied, the potential of the sub-pixel electrode becomes higher than the counter electrode, thus making this sub-pixel positive. In contrast, when a source signal voltage having a negative polarity is supplied, the potential of the sub-pixel electrode becomes lower than the counter electrode, thus making this sub-pixel negative.
The image write pulse of the gate signal supplied to the gate bus line Gj rises, thereby turning ON TFT-1 and TFT-2, and supplying the source signal voltage having the positive polarity to the pixel at jth row, ith column. At this point, the voltage of the liquid crystal capacitor of the first sub-pixel SP-1 is generally equal to the voltage of the liquid crystal capacitor of the second sub-pixel SP-2. Then, the image write pulse of the gate signal supplied to the gate bus line Gj falls, thereby turning OFF TFT-1 and TFT-2.
Next, a control is performed so that the first change of the CS voltage supplied from the CS bus line CS-A to the storage capacitor of the first sub-pixel SP-1 after TFT-1 is turned OFF is an increase, and the first change of the CS voltage supplied from the CS bus line CS-B to the storage capacitor of the second sub-pixel SP-2 after the TFT-2 is turned OFF is a decrease. That is, CS voltages having such waveforms are supplied from the CS bus line CS-A and the CS bus line CS-B. With the positive polarity source signal voltage being supplied to the first sub-pixel SP-1, when the CS voltage supplied from the CS bus line CS-A increases after TFT-1 is turned OFF, the voltage of the liquid crystal capacitor of the first sub-pixel SP-1 increases due to an up-thrusting effect. Therefore, the first sub-pixel SP-1 becomes a bright sub-pixel, which exhibits a higher brightness than that corresponding to the supplied source signal voltage. On the other hand, when the CS voltage supplied from the CS bus line CS-B decreases after TFT-2 is turned OFF, the voltage of the liquid crystal capacitor of the second sub-pixel SP-2 decreases due to a down-thrusting effect. Therefore, the second sub-pixel SP-2 becomes a dark sub-pixel, which exhibits a lower brightness than that corresponding to the supplied source signal voltage. As described above, the viewing angle dependence of the γ characteristics can be improved by displaying a brightness corresponding to the supplied voltage as an average (area average) of two different brightnesses, i.e., by combining different voltage-brightness characteristics (referred to also as the “V-T characteristics”) of two sub-pixels over each other.
A liquid crystal display device having the multi-pixel structure described above uses, as the CS voltage, a voltage having a waveform portion that oscillates with a constant cycle (hereinafter also referred to simply as an “oscillating voltage”). As the size of a liquid crystal display device increases, the load capacitance and resistance of the CS bus line increase. Therefore, the waveform blunting of the CS voltage may vary depending on the position in the display area, and the display brightness may thus be dependent on the position in the display area, thereby causing brightness non-uniformity. Patent Document 3 discloses a liquid crystal display device in which the oscillation cycle of the CS voltage is elongated to thereby suppress/prevent the occurrence of brightness non-uniformity.
Now, referring to FIG. 24 and FIG. 25, the liquid crystal display device disclosed in Patent Document 3 will be described.
FIG. 24(a) is a schematic diagram showing the connections between sub-pixels and CS bus lines, and the polarity and the bright/dark status of each sub-pixel, in the liquid crystal display device disclosed in Patent Document 3. A hatched sub-pixel is a dark sub-pixel, and an unhatched sub-pixel is a bright sub-pixel. A positive polarity sub-pixel is denoted by “+”, and a negative polarity sub-pixel by “−”. FIG. 24(b) shows waveforms of signal voltages in the liquid crystal display device, including, in this order from the top: the CS voltage supplied from the CS bus line CS-B; the source signal voltage supplied to the source bus line Si of the ith column; the gate signal voltage supplied to the gate bus line Gj of the jth row; the voltage applied to one of two sub-pixels included in a pixel corresponding to the source bus line Si of the ith column and the gate bus line Gj of the jth row that has the storage capacitor connected to the CS bus line CS-B, i.e., the sub-pixel P-B(i,j); the gate signal voltage supplied to the gate bus line Gj+1 of the j+1th row; and the voltage applied to one of two sub-pixels of a pixel corresponding to the source bus line Si of the ith column and the gate bus line Gj+1 of the j+1th row that has the storage capacitor connected to the CS bus line CS-B, i.e., the sub-pixel P-B(i,j+1). In the figure, Vcom denotes the counter voltage. Note that the amplitude of the source signal voltage is shown to be constant so as not to overly complicate the description.
As shown in FIG. 24(a), one pixel, e.g., the pixel at jth row, ith column, which is associated with the source bus line Si and the gate bus line Gj, includes a sub-pixel associated with the CS bus line CS-A (it may be designated as “P-A(i,j)”) and a sub-pixel associated with the CS bus line CS-B (it may be designated as “P-B(i,j)”). The pixel at j+1th row, ith column, which is associated with the source bus line Si and the gate bus line Gj+1, includes a sub-pixel associated with the CS bus line CS-B (it may be designated as “P-B(i,j+1)”) and a sub-pixel associated with the CS bus line CS-C (it may be designated as “P-C(i,j+1)”). That is, in the configuration shown in FIG. 24(a), the CS bus line CS-B is commonly associated with two sub-pixels that belong to different pixels and are adjacent to each other in the column direction. As described above, a CS bus line arranged between pixels adjacent to each other in the column direction is commonly associated with two sub-pixels that belong to different pixels and are adjacent to each other in the column direction.
When signal voltages having waveforms shown in FIG. 24(b) are applied, the polarity and the bright/dark status of the sub-pixels are as shown in FIG. 24(a). Herein, dot inversion driving is used so that pixels adjacent to each other in the row direction and the column direction have inverted polarities, and so that bright sub-pixels and dark sub-pixels each form a checkered pattern.
Since a source signal voltage having a positive polarity is supplied to the source bus line Si when the gate signal voltage of the gate bus line Gj is at a high level, the voltage of the sub-pixel P-B(i,j) is positive. Since the first change of the oscillating voltage of the CS bus line CS-B after the gate signal voltage of the gate bus line Gj transitions to a low level is a decrease, the voltage of the sub-pixel P-B(i,j) decreases due to a down-thrusting effect. On the other hand, since the signal voltage of the source bus line Si when the gate signal voltage of the gate bus line Gj+1 is at a high level is negative, the voltage of the sub-pixel P-B(i,j+1) is negative. Since the first change of the oscillating voltage of the CS bus line CS-B after the gate signal voltage of the gate bus line Gj+1 transitions to a low level is a decrease, the voltage of the sub-pixel P-B(i,j+1) decreases due to a down-thrusting effect. At this point, since the voltage of the sub-pixel P-B(i,j+1) is negative, the absolute value of the voltage increases. Therefore, the sub-pixel P-B(i,j) is a dark sub-pixel, and the sub-pixel P-B(i,j+1) is a bright sub-pixel.
FIG. 25(a) is a schematic diagram showing the polarities of source signal voltages supplied to different pixels over two consecutive frames (the Nth frame and the N+1th frame). FIG. 25(b) is a schematic diagram showing the order in which pixels are scanned and the source signal voltage during the scanning over two consecutive frames, showing the waveform of the source signal voltage supplied to the source bus line Si of the ith column and the waveforms of the gate signal voltages supplied to the gate bus lines G1 to Gn of the 1st row to the nth row. A plurality of pixels forming the display area of the liquid crystal display device are successively scanned by the gate signal voltages supplied respectively to the gate bus lines G.
By the dot inversion driving method, source signal voltages of opposite polarities are supplied to pixels that are adjacent to each other in the column direction or the row direction in each of the Nth frame and the N+1th frame, as shown in FIG. 25(a). A so-called frame inversion is also used, whereby the polarities of voltages applied to all pixels are inverted between the Nth frame and the N+1th frame.
With such dot inversion driving, the gate bus lines G1 to Gn are successively selected starting from one end (herein the upper end) of the display area, and pixels are successively selected row by row, both in the Nth frame and in the N+1th frame, as shown in FIG. 25(b). The source signal voltage supplied to the source bus line Si has a waveform in which the polarity is switched every horizontal scanning period (designated as “1H”), and if the brightness of a pixel corresponding to the source bus line Si does not change over two consecutive frames (the Nth frame and the N+1th frame), the phase of the waveform of the source signal voltage during the Nth frame is shifted by 1H from that during the N+1th frame since the amplitude of the source signal voltage remains equal. Although not shown in the figure, the phase of the waveform of the source signal voltage supplied to the source bus line Si+1, which is adjacent to the source bus line Si in the row direction, is shifted by 1H from that of the waveform of the source signal voltage supplied to the source bus line Si. The entire disclosures of Patent Documents 1 to 3 are herein incorporated by reference.
On the other hand, a precharge driving method is known (see, for example, Patent Documents 4 and 5) as a technique for suppressing non-uniformity in the charging of pixel electrodes. With the precharge driving method disclosed in Patent Documents 4 and 5, where the polarity of the source signal voltage is not inverted over a plurality of horizontal scanning periods, a pixel along the jth row is charged in advance by applying a source signal voltage of a value corresponding to a pixel along the j−1th row to the pixel along the jth row before the source signal voltage changes to a value corresponding to the pixel along the jth row, for example, thereby suppressing the charging non-uniformity.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 11-242225    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2004-62146    [Patent Document 3] Japanese Laid-Open Patent Publication No. 2005-189804    [Patent Document 4] Japanese Laid-Open Patent Publication No. 2001-51252    [Patent Document 5] Japanese Laid-Open Patent Publication No. 2003-66928